FIG. 1a shows a depiction of a bus 120. A bus 120 is a “shared medium” communication structure that is used to transport communications between electronic components 101a-10Na and 110a. Shared medium means that the components 101a-10Na and 110a that communicate with one another physically share and are connected to the same electronic wiring 120. Thus, for example, if component 101a wished to communicate to component 10Na, component 101a would send information along wiring 120 to component 10Na; if component 103a wished to communicate to component 110a, component 103a would send information along the same wiring 120 to component 110a, etc.
Computing systems have traditionally made use of busses. With respect to certain IBM compatible PCs, bus 120 may correspond to a PCI bus where components 101a-10Na correspond to “I/O” components (e.g., LAN networking adapter cards, MODEMs, hard disk storage devices, etc.) and component 110a corresponds to an I/O Control Hub (ICH). As another example, with respect to certain multiprocessor computing systems, bus 120 may correspond to a “front side” bus where components 101a-10Na correspond to microprocessors and component 110a corresponds to a memory controller.
In the past, when computing system clock speeds were relatively slow, the capacitive loading on the computing system's busses was not a serious issue because the degraded maximum speed of the bus wiring (owing to capacitive loading) still far exceeded the computing system's internal clock speeds. The same cannot be said for at least some of today's computing systems. With the continual increase in computing system clock speeds over the years, the speed of today's computing systems are reaching (and/or perhaps exceeding) the maximum speed of wires that are heavily loaded with capacitance such as bus wiring 120.
Therefore computing systems are migrating to a “link-based” component-to-component interconnection scheme. FIG. 1b shows a comparative example vis-á-vis FIG. 1a. According to the approach of FIG. 1b, computing system components 101a-10Na (e.g., I/O components, processors) and 110a (e.g., ICH, memory controller) are interconnected through a mesh 140 of high speed bi-directional point-to-point links 1301 through 130N. A bi-directional point-to-point link typically comprises a first unidirectional point-to-point link that transmits information in a first direction and a second unidirectional point-to-point link that transmits information is a second direction that is opposite that of the first direction.
Each point-to-point link can be constructed with copper or fiber optic cabling and appropriate drivers and receivers (e.g., single or differential line drivers and receivers for copper based cables; and LASER or LED E/O transmitters and O/E receivers for fiber optic cables; etc.). The mesh 140 observed in FIG. 1b is simplistic in that each component is connected by a point-to-point link to every other component. In more complicated schemes, the mesh 140 is a network having routing nodes. Here, every component need not be coupled by a point-to-point link to every other component.
Instead, hops across a plurality of links may take place through routing/switching nodes in order to transport information from a source component to a destination component. Depending on implementation, the routing/switching function may be a stand alone function within the network or may be integrated into a substantive component of the computing system (e.g., processor, memory controller, I/O control hub, etc.). According to one perspective, the term “link agent” is used to refer to a component of a link based computing system that includes any such substantive component.